forwardcom forum

This is a proposal for a branch instruction that allows flexible equality comparisons. The proposed branch instruction would have a bitmask, where each bit corresponds to a value of a source register (for example, 32 bit bitmask corresponds to source register range from 0 to 31) - if the correspondi...

The E2 instruction format would even allow for a four input LUT, since it has a 16 bit immediate that can be used as a truth table. That would mean that the destination register would also serve as a source register (A = A AND B AND C AND D) or alternatively, it could be used as a three input LUT wi...

Programs contain many Read Only Arrays/Lookup Tables. Currently they are stored in static data memory. To make a load from such an array, CPU needs to calculate the address as pointer + index and load the value from the dcache. This solution requires a pointer and doesn't exploit locality very well....

"Code and data memory has a 64-bit address space, while we need much less than 2 64 input/output addresses." I'm not so sure. AMD just announced their Smart Access Memory technology, which essentially gives the CPU direct access to the GPU memory (this improves performance in various appli...

What about Western Digitals SweRV? https://github.com/chipsalliance/Cores-SweRV