forwardcom forum

I was thinking today that I don't know why you care about not having page tables and a TLB. What's the problem? It takes hardware resources? So what? Is it really a big a problem to have page tables and TLBs, or is this more of an esthetic preference? One other thing to keep in mind is that you don'...

Apropos of this discussion, Microsoft is rolling out a new segment heap architecture that seems similar in some respects: https://www.blackhat.com/docs/us-16/mat ... ernals.pdf

I just thought of something. Are you familiar with superoptimization and superoptimizing compilers like STOKE? Link: http://stoke.stanford.edu/ STOKE achieves the fastest possible machine code for a given function or other code segment. It's paired with gcc, so it superoptimizes C and C++ code. It e...

Hi Agner – What's the methodology for deciding on the specific instructions to include in the ISA? Is likely application performance a factor? How do you model it or make predictions about likely performance? John Regehr's post on Discovering New Instructions seems relevant and helpful: https://blog...

Hi Agner – The implicit assumption of most ISAs, and of ForwardCom, is that all cores are the same and implement the same instructions. Why? Would there be a benefit of having some cores be simpler, implementing a subset of the ISA? For example, does every core need to support floating point? Or wid...

This reminds me that fast Bezier curve performance would be very useful, without having to worry about being a traditional GPU. Bezier curves are central to a lot of 2D rendering, including fonts and vector graphics like SVG. Some are quadratic and some are cubic. I'm looking into this and it seems...

Hi all — What are the software development implications of the ForwardCom approach to memory management? The approach is summarized here: https://forwardcom.info/#memory_management There was a thread on Agner's blog, but I can't find it. What stood out to me was: the stack being calculated in advanc...

This reminds me that fast Bezier curve performance would be very useful, without having to worry about being a traditional GPU. Bezier curves are central to a lot of 2D rendering, including fonts and vector graphics like SVG. Some are quadratic and some are cubic.

SiFive, the company founded by the academics who designed the RISC-V ISA, has introduced the first Out-of-Order RISC-V core. Some info on the microarchitecture here: https://www.anandtech.com/show/15036/si ... essor-ip/2

Thanks Agner. If it's inefficient on current architectures why do they do it? Do you expect ForwardCom to be faster than x86-64, or would you be using less energy or something? This looks like RISC. You had said at some point that you were drawing from both RISC and CISC approaches? Where is the CIS...

Hi Agner -- What determines if an instruction will require microcode? You had mentioned in the past that you didn't want to use microcode or wanted to minimize the amount of microcode. How is this done? How do you know in advance whether instructions will need microcode?

x86 extended precision is 80 bits: https://en.wikipedia.org/wiki/Extended_ ... ion_format

Is there a broader use of the term "extended precision" that means 128 bits? If so, what do they call the 80-bit form?

Hi Agner -- I suggest that the ForwardCom specification be explicit about compliance or noncompliance with the relevant computational/math standards. You cite IEEE 754-2008 sometimes in the document, but the more comprehensive and international standard is ISO/IEC 10967, which includes not only floa...

Parabix is the most innovative project I've seen using hardware acceleration for string processing: http://parabix.costar.sfu.ca/

They also propose new instructions that would improve upon the SSE 4.2 and AVX-style approaches.

By the way, I'll ask you the same question I asked him. Is there any advantage to treating chars/strings as a basic type in an ISA, instead of treating them as integers? There should be fewer operations possible with them compared to integers – does that knowledge create any opportunities for optimi...

Hi all – I thought this might interest you. It's a "vector-first" ISA: http://www.bitsnbites.eu/the-mrisc32-a- ... pu-design/

Compilers can't generally figure out how to move calculations to a second thread - they can't track all the potential side effects. This applies not only to C++, but also pretty much all higher level languages like Java and Javascript and whatnot. But could compilers be made to have such abilities ...

Hi Agner – How difficult do you anticipate it will be to build an LLVM backend for ForwardCom? This requires compiling LLVM bytecode (or bitcode?) into ForwardCom assembly. Your ideas and constructs are much newer and fresher than LLVM, so I wonder if there might be some fundamental incompatibilitie...

I wonder if it might be a good idea for you to defensively patent critical features or innovations in ForwardCom, while still keeping it public domain: https://arstechnica.com/tech-policy/2018/06/inventor-says-google-is-patenting-work-he-put-in-the-public-domain/ This is Google behaving as it alway...

Hubert, what happens if the second workload is performed on a separate core? For EPIC, I'd assume lots of cores. Compilers can't generally figure out how to move calculations to a second thread - they can't track all the potential side effects. This applies not only to C++, but also pretty much all...

I agree that the patent system is rotten, especially for software. It is not necessary to patent something to prevent others from patenting it. It is sufficient to publish it somewhere. This is true in principle, but I think powerful corporations can sometimes abuse individual inventors. And it's no...

Hi Agner -- After reading this article, I wonder if it might be a good idea for you to defensively patent critical features or innovations in ForwardCom, while still keeping it public domain: https://arstechnica.com/tech-policy/2018/06/inventor-says-google-is-patenting-work-he-put-in-the-public-doma...

Hi Agner -- Have you run any simulations of ForwardCom? Is it possible to determine things like the benefits of not having a TLB with simulations? It's hard to get a sense of whether ForwardCom would be faster or more efficient than x86-64 or ARM64/v8. Given its exclusion of microcode, does the comp...

Hubert, what happens if the second workload is performed on a separate core? For EPIC, I'd assume lots of cores. Separately, does the Mill CPU solve some of these problems? I'm hazy on the details -- didn't the imdepotent processor also address these? I know it's not actually available as a product ...

The common wisdom is that common and simple tasks should be implemented in hardware to make it faster and more energy-efficient. Traditional caches are the consequence of applying this principle to memory management. Scratch-pad memory is software-managed cache. Vendors of cheap processors use it t...