forwardcom forum

I wonder if it might be a good idea for you to defensively patent critical features or innovations in ForwardCom, while still keeping it public domain: https://arstechnica.com/tech-policy/2018/06/inventor-says-google-is-patenting-work-he-put-in-the-public-domain/ This is Google behaving as it alway...

By the way, does 64-bit floating point require 80-bit intermediate values? Would 80-bit immediate constants fit into a 3-word instruction? Architecturally: No. If doing arithmetic in Float64, the programmer always sees a Float64. Internally (at the register transfer level) the floating point number...

What would it take to make our DDR4 bus go away and replace it with a giant L3 cache? Could we make L3 (or L4) a multi-GB thing? What about with stacked or adjacent memories like HBM2 or Hybrid Memory Cube? It can’t be done. A “giant L3 cache” would not longer behave as you would expect from a L3 c...

Yes and no... C has evolved into an abstracted assembly for the collective group of "general purpose 32bit processors" (and their 64bit upgrades), generally covering MIPS and all its clones such as DEC Alpha and Risc V and PA-RISC, x86, ARM, 68k, SPARC, POWER, SuperH. [...] This locks in ...

1. Signed integer overflow: https://kristerw.blogspot.ca/2016/02/how-undefined-signed-overflow-enables.html explains why the do the "exploit" (aka exploit a flaw in the C/C++ specs that was left because of some archaic 36bit-honeywell and ibm-fault-on-overflow hardware) of assuming that i...

The common wisdom is that common and simple tasks should be implemented in hardware to make it faster and more energy-efficient. Traditional caches are the consequence of applying this principle to memory management. Scratch-pad memory is software-managed cache. Vendors of cheap processors use it to...