forwardcom forum

The C++ standard has many cases of 'undefined' behavior which can have quite bad consequences. The ForwardCom design should avoid this and behave in a well-defined and predictable way as far as possible. Here I will propose some solutions to the undefined and unclear situations: 1. Signed integer ov...

Thanks for your detailed analysis. I think it is more efficient to not split instructions into micro-ops. The same entry in the pipeline or reservation station will access address generation unit, read memory operands, wait for missing operands, and go to an execution unit. You are right that the de...

Would the musl C library be the best choice for ForwardCom initially ... ?

Yes, musl looks useful. I intend to write the most common library functions in ForwardCom assembly, the rest might use C code from musl.

JoeDuarte wrote:

Would the complexity of the microcode be affected by limiting FC's virtualization support to identical guest OSes?

Yes. You wouldn't need any hardware support for that - just a subdivision of the memory space.

Hubert wrote: Video games use TONS of floating point math ForwardCom has optional support for half precision floating point vectors. Do you think that video and sound applications can use half precision? Neural networks is another application for half precision. The operand type field in the instruc...

A C++ compiler for ForwardCom is definitely on my wish list. It might be implemented as a back-end to Clang or Gcc. Standard C and C++ programs should compile without problems as long as they don't rely on platform-specific features such as inline assembly or intrinsic functions. Certain things work...

Virtualization requires complex micro-coded instructions. This is something I want to avoid in order to keep the hardware simple and efficient. These features can be added later if needed, but many applications will not need them.

Joe, In a logarithmic number system, multiplication and division become simpler, but addition and subtraction become much more complicated. Your links confirm this. A program with an equal number of additions and multiplications will be faster on a floating point computer than on a logarithmic proce...

Hubert wrote: How many active memory map entries do you think it would be electrically feasible to have on a typical chip? Each entry marking a boundary between memory sections will need one comparator. So the silicon requirement will be somewhat similar to a contents-addressable memory. They can be...

This sounds like an excellent idea, if I understand you right (I am not sure what you mean by "behind" and "over"). We can really gain a lot if we can construct a system with little or no memory fragmentation. We can get rid of the large translation lookaside buffer (TLB) and mul...

Hubert, I have moved your post to the thread "Side-channel attacks". The question is discussed above. A ForwardCom processor will never ignore page faults if it has an on-chip memory map, as I have proposed, because access violation will be detected immediately and this will stop speculati...

This week, there has been a lot of discussion about the newly discovered vulnerability known as side-channel attacks [1]. Most modern superscalar microprocessors have this vulnerability due to their use of speculative execution. The existence of this vulnerability has been confirmed by Intel, AMD, A...

A logarithmic number system is efficient as long as you are using it for multiplication only, but difficult if you want to do addition. You need no extra hardware for multiplying logarithmic numbers - this is simply addition of integers. Another possibility is to use standard floating point numbers ...

I want to add a feature for event handlers. It will work like this: A source code file can define any number of event handlers. Each event handler has a record with the following information: event id, priority, key, and a relative pointer to a function to handle the event. The linker makes a list o...

Author: Agner Date: 2017-04-27 00:03 I am working on the binary utilities for ForwardCom, and I have got an idea of a new concept for function libraries. The well-known method for static linking is used. An option to the linker specifies that certain object files or library files should be re-linka...

Author: yeengief Date: 2017-09-20 14:03 Re variable instruction lengths: Consider some forced alignment, e.g. every 16-byte (or every 32-byte) boundary MUST begin a new instruction. This has minimal impact on the effective code density (if your compiler is not stupid), while allowing almost random ...

Author: Hubert Lamontagne Date: 2017-08-22 12:46 I've taken another quick look today at the specs to figure out how feasible a Verilog implementation running on a FPGA would be, and I'm finding that register file read port counts are on the higher end... 2 ports per AGU (address generating unit), p...

Author: Agner Date: 2017-07-27 02:06 I am working on making an assembler for ForwardCom, and I think that the design of assemblers could use an update, now that we are redesigning everything anyway. I found that it was not too hard to make the assembly syntax look very much like C or Java, rather t...

Author: Joe Duarte Date: 2017-04-13 20:12 FYI, Intel has an upcoming solution for protecting return addresses: https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf It would be interesting to compare ForwardCom's approach to CET. Author: Agner ...

Author: fanoI Date: 2017-03-21 03:41 Agner the code to do an addition between "big integers" that is at page 85 of the forwardcom manual is applicable to any CPU that can do vector integers addition? It could work with x86 using PADDB? This idea is applicable to all other operators (-, *,...

Author: csdt Date: 2017-01-27 10:21 Branch predictors is currently a hard part of a CPU. I propose to help it a bit in the same way we can help the cache: tell it in advance where we want to jump. I think this can be done by a couple of instructions: - chose the destination from 2 immediates based ...

Author: Jonathan Brandmeyer Date: 2017-01-22 23:22 There are a few features of ARM Cortex-M (the microcontroller profile) that I miss when writing system-level programs in other architectures, including Cortex-A/R: - Lack of a control register space. In Cortex-M, the processor's control registers a...

Author: Agner Date: 2017-01-22 04:39 Changes in version 1.05: Systematic description of all instructions. Added chapter: Support for multiple instruction sets. Added chapter: Software optimization guidelines. Bit manipulation instructions improved. Shift instructions can multiply float by power of ...

Author: Agner Date: 2016-12-17 03:39 Joe Duarte wrote: it would be nice to have a detailed comparison of ForwardCom and RISC-V, much of it in the form of comparison tables that get into specific features and decisions. I volunteer to help assemble such a comparison document if you're too busy. Now ...

Author: Joe Duarte Date: 2016-12-14 06:13 Hi Agner. I've been thinking about some interesting research I've read recently, and it raises a couple of questions for me: 1. Does ForwardCom assume synchronous system calls? Could it support a flexible async syscall architecture? I'm not sure where the b...