forwardcom forum

Author: Agner Date: 2016-12-08 03:44 Version 1.04 update today: The instruction formats are made more consistent. Template E2 is modified. The masking principle has been changed. Now there is an option to specify a fallback value to use when a mask bit is zero. The fallback value can be zero, or an...

Author: Hubert Lamontagne Date: 2016-10-28 17:38 Bonus question: How well does ForwardCom handle bilinear interpolation? It's the one algo that I can think of that just doesn't fit well in most CPUs, wastes a bunch of cycles twiddling bits around and generating memory addresses and interpolation fa...

Author: Kurt Baumgardner Date: 2016-09-26 22:00 Ok, here's an idea I haven't heard of: Set up some registers: ProgramID, ThreadID, and ContextID. These are controlled by the CPU and set up by the OS when spawnning a program or thread. The app programmer only has access to ContextID. The bits of eac...

Author: csdt Date: 2016-09-23 12:55 Very interesting project. What if there were a special named register (eg: v0) with a special meaning: - v0 always contains zeroed bits - using v0 as input or output doesn't create any dependency. We could have the same for r0. This would be used to quickly get a...

Author: Kurt Baumgardner Date: 2016-09-09 23:40 I have received this mail from Kurt Baumgardner and I think it belongs on the forum so that others can join the discussion: Hi Agner, My name is Kurt Baumgardner, and I've been reading your processor design draft. Very impressive! Quite obviously a la...

Author: Hubert Lamontagne Date: 2016-09-05 01:53 One recurrent question: How will ForwardCom run Linux's mmap function? Author: Agner Date: 2016-09-05 05:12 You can map a virtual address space as unused, read only, write only, or read/write. In this way you can generate traps on first read and firs...

Author: Agner Date: 2016-08-23 00:24 Two people have sent me this link. Yesterday, ARM announced a future extension with variable vector length: ARM Announces ARM v8-A with Scalable Vector Extensions http://www.anandtech.com/show/10586/arm-announces-arm-v8a-with-scalable-vector-extensions-aiming-fo...

Author: Joe Duarte Date: 2016-08-04 01:23 Agner, there are a couple of specialized instruction domains that you seem to be pushing to FPGAs or other coprocessors, but I think ForwardCom will suffer from their exclusion. Encryption may be specialized, but it's not optional anymore. Fast encryption i...

Author: Agner Date: 2016-08-01 01:48 I have made an introduction to the ForwardCom project at http://www.forwardcom.info. I have added a few optional instructions to facilitate matrix multiplication. Author: EricTL Date: 2017-07-17 18:15 Great proposal so far with a lot of interesting ideas. May I ...

Author: Agner Date: 2016-07-29 07:51 Anonymous wrote: Many algorithms use matrix multiplication, which can greatly benefit from instruction-level parallelism, but the current instructions sets are simply disappointing [...] it's simply not possible to express it nicely with the instructions given b...

Author: Anonymous Date: 2016-07-28 07:10 Agner, have you studied the MIPS architecture? What do you think of "branch delay slots" ? Personally, I like them, because of the following: There are things the software developer (and the compiler) easily knows, but the hardware developer will h...

Author: Joe Duarte Date: 2016-08-17 23:46 Agner wrote: Joe Duarte wrote: I think it would be interesting if applications could set a few custom constants at start time. A while back I asked about having useful constants hardwired in the CPU (e.g. π), and you guys explained why it probably wouldn't ...

Author: Sylvain Collange Date: 2016-08-18 10:20 Agner wrote: Can you bypass a result to multiple in-flight instructions using the same bus? If so, you need only few bypass buses. Yes, that is essentially how it is done (or at least how it is described in textbooks). But the load on the bus increase...

Author: Sylvain Collange Date: 2016-08-15 04:00 Agner wrote: My reason for using the same registers for floating point scalars and floating point vectors is that floating point code often contains calls to mathematical function libraries. Such a library can use variable-length vectors for parameter...

Author: Agner Date: 2016-06-26 02:48 The discussion in the thread Proposal for an ideal extensible instruction set has been very fruitful and led to a lot of new ideas. I don't know where this will lead us, but the project looks so promising that it is worth pursuing further. I have put the project...

I have now moved this project to Github as some of you recommended. This will facilitate the collective development of software toolchain and hardware implementation. The name CRISC was taken, so I have changed the name to ForwardCom. It stands for forward compatible computer system. I have converte...

Author: Agner Date: 2016-06-05 13:26 In the beginning of this thread I argued against having a link register. Storing return addresses on the stack is simpler. Now I wonder if it is better to have two stacks: a call stack for return addresses and a data stack for the local variables of functions. T...

Author: Agner Date: 2016-05-20 05:07 Windows systems use dynamic link libraries (DLLs) and Unix-like systems (Linux, BSD, Mac OS) use shared objects (SOs). Both types have a number of disadvantages. I have an idea for replacing DLLs and SOs with something more efficient in the new CRISC architectur...

Author: Agner Date: 2016-06-02 05:16 Harry wrote: Could I suggest that you move the development incl. discussions of CRISC to GitHub instead? You are right. This project has developed to more than I initially expected and it is approaching a level where it makes sense to move it to a public reposit...

Author: Agner Date: 2016-05-10 10:28 The instruction set specification is now updated to version 1.01: www.agner.org/optimize/instructionset.pdf The instruction set has got the name CRISC1 to indicate the compromise between RISC and CISC. All user-level instructions are now defined. The most import...

Author: zboson Date: 2016-04-11 03:24 Hi, I think it might be worth considering other three operand single rounding mode instructions besides FMA. As I discovered here http://stackoverflow.com/questions/30573443/optimize-for-fast-multiplication-but-slow-addition-fma-and-doubledouble double-double m...

Author: A-11 Date: 2016-04-10 07:35 It should be too late. but since I found a research today, I ask for it. BOOST: Berkeley's Out-of-Order Stack Thingy https://www.researchgate.net/publication/228556746_BOOST_Berkeley's_Out-of-Order_Stack_Thingy Same as "register renaming" for register m...

Author: Hubert Lamontagne Date: 2016-04-02 14:13 Agner wrote: Thank you for your comments. It is nice to have sparring partners to discuss with. We are really getting somewhere. Ha yeah. "Sparring partner" is a great way to put it. :3 I think there are many advantages to storing the vecto...

Author: Agner Date: 2016-03-31 01:55 An alternative to two register outputs for add-with-carry is to have extra carry bits in the register. We could, for example, have one extra flag bit for each 32 bits of vector registers. The extra bit can be used for carry, overflow, masks, etc. In this way we ...

Author: Agner Date: 2016-03-22 10:51 Thank you everybody for all your inspiring comments to my "Proposal for an ideal extensible instruction set". I have now worked everything together and made a more detailed proposal. It is published at http://www.agner.org/optimize/instructionset.pdf I...