Search found 185 matches
- 2019-01-28, 15:18:28
- Forum: forwardcom forum
- Topic: Range/Interval based floating point computation
- Replies: 1
- Views: 8276
Re: Range/Interval based floating point computation
It is possible to change the rounding mode globally using the Numeric control register, or for an individual instruction or even for a single vector element using a mask register.
- 2019-01-24, 17:34:37
- Forum: forwardcom forum
- Topic: Computational standards compliance
- Replies: 3
- Views: 11088
Re: Computational standards compliance
80 bit float is not mentioned in the IEEE standard. It was introduced with the Intel 8087 coprocessor and AFAIK used only in Intel-compatible processors.
The IEEE standard mentions the following floating point types: binary16, binary32, binary64, binary128.
The IEEE standard mentions the following floating point types: binary16, binary32, binary64, binary128.
- 2019-01-21, 19:56:54
- Forum: forwardcom forum
- Topic: Computational standards compliance
- Replies: 3
- Views: 11088
Re: Computational standards compliance
The intention is to support IEEE-754 in the form of the next revision forthcoming in 2019. Among the forthcoming changes to IEEE-754 is a sanitation of the max and min functions for NAN inputs. Subnormal numbers may be turned off by default for performance reasons. They are very costly to support. T...
- 2018-12-17, 13:36:04
- Forum: forwardcom forum
- Topic: Handling paging without a page system
- Replies: 3
- Views: 11658
Re: Handling paging without a page system
There are no fixed-size pages. The OS would have to make an arbitrary-size entry in the memory map for a block of memory that has been swapped to disk.
- 2018-09-30, 4:36:28
- Forum: forwardcom forum
- Topic: Protection against spambots
- Replies: 0
- Views: 28639
Protection against spambots
There has been a lot of spam posting here lately. Apparently the security question was too easy to answer for spambots. Now I have changed the security question to make it more difficult. The answer is a single word.
- 2018-08-26, 9:27:26
- Forum: forwardcom forum
- Topic: Interesting new ISA: MRISC32
- Replies: 13
- Views: 28564
Re: Interesting new ISA: MRISC32
mbitsnbites wrote: The most common problem is zero-terminated strings. With naive instructions this becomes a data dependent branched loop, where the content of every byte needs to be inspected, and it's impossible for the CPU to correctly predict the final branch. This problem has already been solv...
- 2018-08-26, 5:30:30
- Forum: forwardcom forum
- Topic: Interesting new ISA: MRISC32
- Replies: 13
- Views: 28564
Re: Interesting new ISA: MRISC32
mbitsnbites wrote: in my design I need to know the vector operation length before accessing the vector register file. I have the vector register fetch in one pipeline stage, and I have the vector register element indexing logic in the pipeline stage before that. I have solved that problem by requiri...
- 2018-08-25, 5:03:06
- Forum: forwardcom forum
- Topic: Interesting new ISA: MRISC32
- Replies: 13
- Views: 28564
Re: Interesting new ISA: MRISC32
Thanks for the link. The MRISC32 ISA has some of the same ideas as ForwardCom. Maybe there is a basis for collaboration. I have added my comment at http://www.bitsnbites.eu/the-mrisc32-a- ... ent-219160
- 2018-07-20, 6:06:33
- Forum: forwardcom forum
- Topic: Is ForwardCom LLVM-friendly
- Replies: 2
- Views: 13505
Re: Is ForwardCom LLVM-friendly
LLVM would be my first choice for a compiler for ForwardCom. I haven't had the time to look into it, so I don't know if there are any obstacles. The variable-length vectors and vector loops might be a problem.
- 2018-07-03, 5:19:59
- Forum: forwardcom forum
- Topic: Forwardcom and caching models
- Replies: 15
- Views: 34961
Re: Forwardcom and caching models
But could compilers be made to have such abilities? Forget the past -- what about now? Yes. For example the Intel compiler can put prefetching of data into a separate thread running in the same CPU core with simultaneous multithreading (= hyperthreading in Intel lingo). I generally don't like simul...
- 2018-06-28, 5:46:52
- Forum: forwardcom forum
- Topic: Forwardcom and patents
- Replies: 4
- Views: 14871
Re: Forwardcom and patents
In my opinion, the patent system as it works today is rotten. The patent system is intended to stimulate invention and innovation, but today it is doing the opposite. Hi tech companies are filing scores of patents, not to protect their inventions but for having weapons to use in patent wars. For exa...
- 2018-06-13, 17:26:26
- Forum: forwardcom forum
- Topic: Forwardcom simulations
- Replies: 3
- Views: 13173
Re: Forwardcom simulations
The tools that I have developed so far can emulate the ForwardCom processor but not simulate memory latencies. The instruction set is designed for making OoO execution efficient. The compiler does not need to do this. Only the old x87 instructions use 80-bit intermediaries. Most other instruction se...
- 2018-05-24, 11:07:49
- Forum: forwardcom forum
- Topic: NAN propagation instead of fault trapping. Can we avoid speculative execution?
- Replies: 3
- Views: 15157
NAN propagation instead of fault trapping. Can we avoid speculative execution?
Floating point calculations can generate infinity (INF) and not-a-number (NAN) in case of errors. These codes will propagate to the end result of a sequence of calculations in most cases. This is a convenient way of detecting floating point errors, and it is more efficient than using traps (software...
- 2018-05-20, 5:10:35
- Forum: forwardcom forum
- Topic: Forwardcom and caching models
- Replies: 15
- Views: 34961
Re: Forwardcom and caching models
ForwardCom could use any caching model. Experiments with alternative forms of caching are welcome. I don't think that 128 kB would be enough if you have large vector registers, but the cache might be subdivided into 'lanes' that align with the data lanes of the CPU. Quoting from the manual: The Forw...
- 2018-04-21, 6:01:23
- Forum: forwardcom forum
- Topic: One flexible register
- Replies: 1
- Views: 11000
Re: One flexible register
The difference between a vector register and a scalar register is that you can handle the entire vector register with a single operation. If you want to add 1 to four 32-bit registers you need four instructions. If you want to add 1 to all four elements of a 128 bit vector register you only need one...
- 2018-04-14, 9:23:01
- Forum: forwardcom forum
- Topic: Emulating multiple output instructions with caching
- Replies: 6
- Views: 15372
Re: Emulating multiple output instructions with caching
csdt wrote: the multiple instruction scheme is also applicable to the division (just call div and rem) Yes, but not to extended division (divide a 64 bit integer by a 32 bit integer to get a 32 bit quotient and a 32 bit remainder). is there any performance critical codes that require to compute div ...
- 2018-04-13, 19:03:49
- Forum: forwardcom forum
- Topic: Emulating multiple output instructions with caching
- Replies: 6
- Views: 15372
Re: Emulating multiple output instructions with caching
csdt wrote: Back on the add with carry, is it really necessary to have a single instruction to get both the result and the carry? It might be worth considering recalculating the sum to get the carry. An integer addition is pretty fast, so recalculating it would not incur too much overhead. That's po...
- 2018-04-13, 10:43:43
- Forum: forwardcom forum
- Topic: Emulating multiple output instructions with caching
- Replies: 6
- Views: 15372
Re: Emulating multiple output instructions with caching
The ForwardCom instruction set has 'mul' instructions which give the low part of a product, 'mul_hi' gives the high part, and 'mul_ex' gives double-size products as a vector. Vector elements with even-numbered position (0, 2, 4, ..) contain the low parts while odd elements (1, 3, 5, ..) contain the ...
- 2018-03-30, 17:28:39
- Forum: forwardcom forum
- Topic: All the tools are working now
- Replies: 0
- Views: 26455
All the tools are working now
All the binary tools for ForwardCom are working now: assembler, disassembler, linker, library manager, emulator, debugger. These tools can run in Windows and Linux. I have also made function libraries: libc.li contains the most important standard C functions. A library of mathematical functions math...
- 2018-03-14, 20:19:15
- Forum: forwardcom forum
- Topic: Forwardcom possible execution pipeline?
- Replies: 11
- Views: 21272
Re: Forwardcom possible execution pipeline?
Yes, but not for multiplication and division. I don't want to have ALU operations with different latencies combined with conditional jump because it will complicate the pipeline.
- 2018-03-11, 5:32:26
- Forum: forwardcom forum
- Topic: Forwardcom possible execution pipeline?
- Replies: 11
- Views: 21272
Re: Forwardcom possible execution pipeline?
The C language is particularly bad for overflow checking. It's not safe to detect signed integer overflow after it has occurred because the compiler is allowed to optimize it away. I've seen a very nasty bug because I checked for overflow in this way. See https://codereview.stackexchange.com/questio...
- 2018-03-10, 5:44:53
- Forum: forwardcom forum
- Topic: Forwardcom possible execution pipeline?
- Replies: 11
- Views: 21272
Re: Forwardcom possible execution pipeline?
Regarding integer fault traps. Yes, I would love to avoid fault trapping for both integer and floating point calculations altogether. In addition to the problems that Hubert point to, there is the problem that the behavior depends on vector length. A trap may happen at different times in a loop sequ...
- 2018-03-05, 12:32:25
- Forum: forwardcom forum
- Topic: Decimal floating point
- Replies: 3
- Views: 10985
Re: Decimal floating point
Why would a financial application need decimal floating point? You can get exactness just by multiplying by 100 so that you are counting cents rather than $ or € or whatever. BTW, the x86 instruction set has instructions for decimal numbers but they were never used, so they have been removed in x86-...
- 2018-03-04, 10:21:02
- Forum: forwardcom forum
- Topic: Decimal floating point
- Replies: 3
- Views: 10985
Re: Decimal floating point
I prefer computers to use binary numbers. This is more efficient. The standards for decimal floating point numbers are certainly not easier to deal with than binary.
- 2018-02-25, 10:36:39
- Forum: forwardcom forum
- Topic: Forwardcom possible execution pipeline?
- Replies: 11
- Views: 21272
Re: Forwardcom possible execution pipeline?
Thank you Kulasko.
This is very similar to what I have in mind. The number of parallel units may wary of course. Memory write may be after the ALU's, but there are few, if any, instructions that use both ALU and memory write.
This is very similar to what I have in mind. The number of parallel units may wary of course. Memory write may be after the ALU's, but there are few, if any, instructions that use both ALU and memory write.