forwardcom forum

Congratulations with your thesis, Kulasko.
Officially, it is 'just' a bachelor thesis, but in reality it is the result of six years of work. A very impressive achievement!
Thank you for your work. I hope you will continue...

Do we need an organization to manage the ForwardCom project? Such an organization could help people get involved, organize online meetings and conferences, facilitate research projects, develop standards, etc. The idea of an organization came up as I was trying to find a solution to the problem of c...

@Moonchild It is too complex for a single instruction. It requires many additions and horizontal data transfer across vector lanes. The latency would depend on the vector length. People could propose a zillion other functions that they would like to implement in hardware, including elementary mathem...

@Moonchild:
Sum scan of an array is a complex instruction with long data-dependent latency. This would require microcode. ForwardCom avoids microcode.

Good idea, Hubert I have thought about a cheaper solution, though less universal. ForwardCom is intended to avoid memory fragmentation. In small systems and embedded systems you may not need demand paged memory. If you don't have demand paging you don't need to be able to recover from memory access ...

Moonchild wrote:

vector sum scan instruction

I don't understand what you mean. The manual explains how to make a horizontal vector sum.

Moonchild wrote:

One-off bit operations

There are instructions for set, clear, toggle, and test a single bit or multiple bits. There is bit scan, popcount, and bitfield manipulation. What else do you need?

The FPGA softcore has now been developed to a stage where all integer instructions work. This includes complicated instructions such as: multiplication, multiplication high part, multiply and add, division with a choice of rounding modes, remainder, push/pop a sequence of registers with a choice of ...

Hi Webenson What you propose is indeed the solution I have implemented. Performance counter number 16 will count various errors and show the code address where the first error occurred. This is a cheap solution to implement in hardware. Division by 0 gives INT_MAX, INT_MIN, or UINT_MAX. Returning 0 ...

You are right that speculation is quite expensive in terms of hardware. ForwardCom needs less speculation because there are no numerical error traps. A processor with out-of-order capabilities but no speculation might be attractive. (It could decode both sides of a 2-way branch to reduce pipeline bu...

Hubert, the idea of a priority hint makes sense. A NOP instruction has many unused bits that can be used as various hints. On the other hand, if the compiler knows which instructions should have high priority, it would simply put these instructions first. An out-of-order processor will reorder instr...

Hubert, a % b = a will satisfy a % b == a - (a/b)*b in all cases. There is a modulo instruction, and it is easy to implement because the existing division hardware gives the remainder as well, whether you need it or not. I have considered to make division by 0 give 0, but this would increase the ris...

I have almost finished making the division hardware for the ForwardCom softcore (using a radix-4 division loop). Now I have to decide what to do with integer division by zero. I have tried to google what other microprocessors do with integer division by zero. X86 makes an error trap. ARM and PowerPC...

Thank you for your comments. Regarding speculative read The proposed speculative read should be a special instruction for this purpose. Advantages: no waste of RAM for padding space. Disadvantages: messy hardware logic; does not allow all addressing modes. The alternative is to insert a padding spac...

I am beginning to work on version 1.12 of ForwardCom. I have several proposals for changes that I will open up for discussion: 1. Speculative memory read I would like an option for reading from memory without causing a trap in case the address is invalid. A read from an illegal address should produc...

This looks very exciting. I am looking forward to see your results.

Your multicore sieve of Eratosthenes would be very expensive to implement in hardware because the data cache needs to combine single bits from each core.

ForwardCom has many instructions for bit manipulation including instructions to extract, insert, or move bit fields with an arbitrary number of bits in each element. This allows efficient packing of information. If you have many booleans then it is most efficient to make bit vectors that can handle ...

I am somewhat skeptical too. CHERI is proposing a very costly solution to a problem that can be solved in other ways. I haven't looked too deeply into CHERI, but as I understand it, it requires a lot of changes in both hardware and software: The hardware ISA must have an extra set of special 128-bit...

does that mean there is no BTB cost for forward never-taken branches?

On some processors, yes.

Isn't this a case where forwardcom would do much better than traditional cpus? Because the call stack is expressed explicitly, it is the same as the return prediction stack. So after you install a new call stack, you maybe pipeline stall, but then start start predicting returns correctly from it. Y...

Thank you for trying to find weak points in my system. I think that nonlocal returns may be implemented more efficiently as a sequence of normal returns. 1. Why? Why is it more efficient to return multiple times than just once? Because it doesn't mess up the return prediction. A non-local return wil...

I think that nonlocal returns may be implemented more efficiently as a sequence of normal returns. It is possible to have multiple data stacks on ForwardCom. The compiler could use a register or an extra stack or a particular stack space to keep track of the nesting level. Error handling can also be...

You are right that stack unwinding requires privileged instructions. Stack unwinding takes place in the following cases: Exception trapping (try/catch) in object oriented languages Debugging longjmp in C Exception trapping and debugging require privileged access anyway. A program that has a large nu...

The more fragmented the memory becomes, the more complicated becomes the access: In simple cases where there are few processes running and plenty of vacant RAM, you don't need any address translation. All you need is a small memory map with a few variable-size entries. This memory map can stay on-ch...