forwardcom forum

Current systems are allocating memory blocks of 4kB each - sometimes bigger. I want to avoid the fixed-size blocks. With 4GB RAM you will have a million 4kB blocks. Such a huge page table may be too big to fit on the chip. You may have nested page tables and other complexities. In current systems, a...

These methods are intended to reduce memory fragmentation. You don't need more RAM. Current systems have large page tables and a translation lookaside buffer (TLB). These pages are taking a lot of hardware and software resources. If you don't have memory fragmentation you don't need page tables. You...

I have finally allocated time to do an FPGA implementation of ForwardCom. Can you mention some good examples of softcores that I can use as a starting template?

I have finally decided for method 2 mentioned above. This is now fully implemented in version 1.09 of the emulator and documented in the manual. This method makes sure that the detection of an exception is tied to the output of the specific instruction. The result of an exception is either the defau...

I agree that loop unrolling can be a bad thing. It is a waste of code cache. Compilers are often unrolling loops excessively. Intel CPUs do indeed have a buffer similar to what you are proposing. In fact, they have two. There is a loopback buffer that can recycle decoded instructions after the decod...

Kulasko wrote: Presumably, decoders don't have a constant latency and output just zero or one operation per clock, but n operations. If an instruction generates two µ-ops, then you can put the second one in a pending position and stall the decoder in the next clock cycle. You can do the same with a ...

Thanks for your analysis. The ABI guarantees that you can read a maximum vector length beyond the actual data without going into non-available memory. The restore of a variable-length vector could take advantage of this and use a single read of the size of a length-specifier plus the maximum vector ...

I have never worked with graphic processing, but this is certainly worth doing. You could either use the FPGA feature to make custom instructions or make it hard coded. Do the instructions have long latency?

Thank you for looking at this.

This instruction is so important that it is worth some extra hardware. I am imagining a state machine for this instruction. You don't have to use any advanced data compression algorithm, just adjust the length so that unused register bits are not saved/restored.

Thanks for the advice. I think that https://opencores.org/ is the place to host the project and look for help. I am just too busy with other projects to start it up right now.

Thank you for reporting this problem.

Now I have updated the code and fixed a problem with Linux. Does it work now?

Thanks for your interest. All the tools are there, including emulator. What may confuse you is that all the tools are combined into a single executable file. See the manual for how to use it. You can find a windows executable in forw.zip. In other operating systems, you have to compile the executabl...

This discussion is continued in a new thread. Different ways of detecting floating point exceptions and errors are discussed here: viewtopic.php?f=1&t=124

It is all on https://www.forwardcom.info and in the manual https://github.com/ForwardCom/manual/raw/master/forwardcom.pdf . I think it is too early to write papers about it. Forwardcom is currently a one man project and I am busy with other projects right now. That's why progress goes slowly. It wou...

No, this is in a development stage. It has not been coded on an FPGA yet. Any help with this will be appreciated.

Floating point errors are traditionally detected in two ways: with a global status register or by traps (software interrupts). Both methods are problematic with out-of-order execution and vector processing (SIMD) for the following reasons. A global status register has to be updated after every float...

The x86 instruction set has developed through many years. What was optimal in the 1980s is not optimal today, but today's processors have to be backward compatible with everything that has been added through the years. For example, it is faster to calculate a sine using a function library, but you s...

Microprocessors generally use microcode for complex instructions that are doing complex things, or a sequence of multiple things. Typical examples are: Instructions that save or restore all registers on task switches Mathematical functions such as sin and cos Gather and scatter The microcode works l...

It is possible to change the rounding mode globally using the Numeric control register, or for an individual instruction or even for a single vector element using a mask register.

80 bit float is not mentioned in the IEEE standard. It was introduced with the Intel 8087 coprocessor and AFAIK used only in Intel-compatible processors.
The IEEE standard mentions the following floating point types: binary16, binary32, binary64, binary128.

The intention is to support IEEE-754 in the form of the next revision forthcoming in 2019. Among the forthcoming changes to IEEE-754 is a sanitation of the max and min functions for NAN inputs. Subnormal numbers may be turned off by default for performance reasons. They are very costly to support. T...

There are no fixed-size pages. The OS would have to make an arbitrary-size entry in the memory map for a block of memory that has been swapped to disk.

There has been a lot of spam posting here lately. Apparently the security question was too easy to answer for spambots. Now I have changed the security question to make it more difficult. The answer is a single word.

mbitsnbites wrote: The most common problem is zero-terminated strings. With naive instructions this becomes a data dependent branched loop, where the content of every byte needs to be inspected, and it's impossible for the CPU to correctly predict the final branch. This problem has already been solv...

mbitsnbites wrote: in my design I need to know the vector operation length before accessing the vector register file. I have the vector register fetch in one pipeline stage, and I have the vector register element indexing logic in the pipeline stage before that. I have solved that problem by requiri...