Search found 185 matches
- 2020-05-16, 5:18:17
- Forum: forwardcom forum
- Topic: Proposal to drop tiny instructions
- Replies: 11
- Views: 30528
Re: Proposal to drop tiny instructions
I think it was you who advised me four years ago to avoid multi-output instructions. Now that I have started to work with a soft core I can see that you were right. It is good to reduce the number of register write ports and result buses. But splitting an instruction into multiple µops appears to be...
- 2020-05-16, 4:50:11
- Forum: forwardcom forum
- Topic: Methodology for choosing instructions to include or omit
- Replies: 2
- Views: 6609
Re: Methodology for choosing instructions to include or omit
Thanks for the link. The x86-64 ISA has thousands of instructions. In fact, my x86 disassembler has a table of 2029 instructions. It is miraculous that Intel and AMD have actually managed to put all this on a single silicon chip and still get a good performance, but it is obviously not an optimal de...
- 2020-05-14, 12:58:47
- Forum: forwardcom forum
- Topic: Proposal to drop tiny instructions
- Replies: 11
- Views: 30528
Proposal to drop tiny instructions
At present, ForwardCom has four different instruction sizes. Most instructions use a single 32-bit code word. Instructions that need extra bits for constants, extra registers, extra option bits, etc. can use two or three 32-bit words. There is also a tiny instruction format. Two tiny instructions ca...
- 2020-05-13, 12:32:27
- Forum: forwardcom forum
- Topic: Separate call stack and data stack
- Replies: 6
- Views: 12641
Separate call stack and data stack
I have written in the specifications that it is recommended to have two separate stacks - a call stack for return addresses, and a data stack for local data. This was for security reasons to prevent buffer overflow attacks. Now I have found another advantage of separate stacks. While making the inst...
- 2020-05-06, 5:21:14
- Forum: forwardcom forum
- Topic: Heterogenous cores / instruction sets
- Replies: 3
- Views: 7928
Re: Heterogenous cores / instruction sets
I have started to make a softcore for an FPGA (Artix 7). In this early stage, I am using only on-chip RAM so I don't need 64 bit addresses. But integer registers should probably be 64 bits anyway for the sake of compatibility. I guess it will be configurable so that you can choose floating point sup...
- 2020-05-06, 5:10:56
- Forum: forwardcom forum
- Topic: Implications of ForwardCom memory management approach
- Replies: 15
- Views: 27353
Re: Implications of ForwardCom memory management approach
Maybe I should be more clear about local heap and global heap. The local heap is owned and managed by the program. The global heap belongs to the OS. A well-behaved program will ask the OS to allocate a big chunk of memory from the global heap and use it for its local heap. If the program has linked...
- 2020-05-05, 5:35:33
- Forum: forwardcom forum
- Topic: Heterogenous cores / instruction sets
- Replies: 3
- Views: 7928
Re: Heterogenous cores / instruction sets
Yes, that would certainly be useful. Especially if the OS can know in advance whether a new process or a new thread needs the extra resources, so that it wouldn't have to jump to another core in case a thread has been started in a core that doesn't fit its needs.
- 2020-05-05, 5:29:45
- Forum: forwardcom forum
- Topic: Implications of ForwardCom memory management approach
- Replies: 15
- Views: 27353
Re: Implications of ForwardCom memory management approach
Current systems are allocating memory blocks of 4kB each - sometimes bigger. I want to avoid the fixed-size blocks. With 4GB RAM you will have a million 4kB blocks. Such a huge page table may be too big to fit on the chip. You may have nested page tables and other complexities. In current systems, a...
- 2020-05-02, 4:29:18
- Forum: forwardcom forum
- Topic: Implications of ForwardCom memory management approach
- Replies: 15
- Views: 27353
Re: Implications of ForwardCom memory management approach
These methods are intended to reduce memory fragmentation. You don't need more RAM. Current systems have large page tables and a translation lookaside buffer (TLB). These pages are taking a lot of hardware and software resources. If you don't have memory fragmentation you don't need page tables. You...
- 2020-04-26, 6:57:37
- Forum: forwardcom forum
- Topic: Putting it on real hardware
- Replies: 7
- Views: 17206
Re: Putting it on real hardware
I have finally allocated time to do an FPGA implementation of ForwardCom. Can you mention some good examples of softcores that I can use as a starting template?
- 2020-04-26, 6:44:28
- Forum: forwardcom forum
- Topic: More efficient ways of detecting exceptions
- Replies: 1
- Views: 12993
Re: More efficient ways of detecting exceptions
I have finally decided for method 2 mentioned above. This is now fully implemented in version 1.09 of the emulator and documented in the manual. This method makes sure that the detection of an exception is tied to the output of the specific instruction. The result of an exception is either the defau...
- 2020-04-18, 5:34:36
- Forum: forwardcom forum
- Topic: What about optimising for faster loops?
- Replies: 1
- Views: 7162
Re: What about optimising for faster loops?
I agree that loop unrolling can be a bad thing. It is a waste of code cache. Compilers are often unrolling loops excessively. Intel CPUs do indeed have a buffer similar to what you are proposing. In fact, they have two. There is a loopback buffer that can recycle decoded instructions after the decod...
- 2020-04-06, 17:12:35
- Forum: forwardcom forum
- Topic: Possible difficulties for microcode-less implementations
- Replies: 8
- Views: 17227
Re: Possible difficulties for microcode-less implementations
Kulasko wrote: Presumably, decoders don't have a constant latency and output just zero or one operation per clock, but n operations. If an instruction generates two µ-ops, then you can put the second one in a pending position and stall the decoder in the next clock cycle. You can do the same with a ...
- 2020-04-02, 4:47:12
- Forum: forwardcom forum
- Topic: Possible difficulties for microcode-less implementations
- Replies: 8
- Views: 17227
Re: Possible difficulties for microcode-less implementations
Thanks for your analysis. The ABI guarantees that you can read a maximum vector length beyond the actual data without going into non-available memory. The restore of a variable-length vector could take advantage of this and use a single read of the size of a length-specifier plus the maximum vector ...
- 2020-03-22, 5:36:31
- Forum: forwardcom forum
- Topic: Using Forwardcom as a GPU?
- Replies: 11
- Views: 18174
Re: Using Forwardcom as a GPU?
I have never worked with graphic processing, but this is certainly worth doing. You could either use the FPGA feature to make custom instructions or make it hard coded. Do the instructions have long latency?
- 2020-03-06, 9:18:07
- Forum: forwardcom forum
- Topic: Possible difficulties for microcode-less implementations
- Replies: 8
- Views: 17227
Re: Possible difficulties for microcode-less implementations
Thank you for looking at this.
This instruction is so important that it is worth some extra hardware. I am imagining a state machine for this instruction. You don't have to use any advanced data compression algorithm, just adjust the length so that unused register bits are not saved/restored.
This instruction is so important that it is worth some extra hardware. I am imagining a state machine for this instruction. You don't have to use any advanced data compression algorithm, just adjust the length so that unused register bits are not saved/restored.
- 2020-02-12, 5:35:11
- Forum: forwardcom forum
- Topic: Putting it on real hardware
- Replies: 7
- Views: 17206
Re: Putting it on real hardware
Thanks for the advice. I think that https://opencores.org/ is the place to host the project and look for help. I am just too busy with other projects to start it up right now.
- 2020-02-08, 11:28:08
- Forum: forwardcom forum
- Topic: Current status of bintools
- Replies: 4
- Views: 10191
Re: Current status of bintools
Thank you for reporting this problem.
Now I have updated the code and fixed a problem with Linux. Does it work now?
Now I have updated the code and fixed a problem with Linux. Does it work now?
- 2020-02-07, 6:12:00
- Forum: forwardcom forum
- Topic: Current status of bintools
- Replies: 4
- Views: 10191
Re: Current status of bintools
Thanks for your interest. All the tools are there, including emulator. What may confuse you is that all the tools are combined into a single executable file. See the manual for how to use it. You can find a windows executable in forw.zip. In other operating systems, you have to compile the executabl...
- 2020-02-04, 6:38:51
- Forum: forwardcom forum
- Topic: NAN propagation instead of fault trapping. Can we avoid speculative execution?
- Replies: 3
- Views: 15166
Re: NAN propagation instead of fault trapping. Can we avoid speculative execution?
This discussion is continued in a new thread. Different ways of detecting floating point exceptions and errors are discussed here: viewtopic.php?f=1&t=124
- 2020-02-04, 5:20:24
- Forum: forwardcom forum
- Topic: Putting it on real hardware
- Replies: 7
- Views: 17206
Re: Putting it on real hardware
It is all on https://www.forwardcom.info and in the manual https://github.com/ForwardCom/manual/raw/master/forwardcom.pdf . I think it is too early to write papers about it. Forwardcom is currently a one man project and I am busy with other projects right now. That's why progress goes slowly. It wou...
- 2020-02-03, 5:29:09
- Forum: forwardcom forum
- Topic: Putting it on real hardware
- Replies: 7
- Views: 17206
Re: Putting it on real hardware
No, this is in a development stage. It has not been coded on an FPGA yet. Any help with this will be appreciated.
- 2020-02-02, 7:46:04
- Forum: forwardcom forum
- Topic: More efficient ways of detecting exceptions
- Replies: 1
- Views: 12993
More efficient ways of detecting exceptions
Floating point errors are traditionally detected in two ways: with a global status register or by traps (software interrupts). Both methods are problematic with out-of-order execution and vector processing (SIMD) for the following reasons. A global status register has to be updated after every float...
- 2019-02-19, 5:56:15
- Forum: forwardcom forum
- Topic: How to know if an instruction requires microcode
- Replies: 3
- Views: 11362
Re: How to know if an instruction requires microcode
The x86 instruction set has developed through many years. What was optimal in the 1980s is not optimal today, but today's processors have to be backward compatible with everything that has been added through the years. For example, it is faster to calculate a sine using a function library, but you s...
- 2019-02-17, 5:53:58
- Forum: forwardcom forum
- Topic: How to know if an instruction requires microcode
- Replies: 3
- Views: 11362
Re: How to know if an instruction requires microcode
Microprocessors generally use microcode for complex instructions that are doing complex things, or a sequence of multiple things. Typical examples are: Instructions that save or restore all registers on task switches Mathematical functions such as sin and cos Gather and scatter The microcode works l...