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New softcore

Posted: 2021-08-08, 11:31:07
by agner
I have been working hard on developing a softcore implementation of ForwardCom,
and I am now proud to publish the first version on Github.

Features:
  • Implemented on Nexys A7 FPGA board with Xilinx Artix 7 100T FPGA
  • Coded in System Verilog with an open license
  • Everything is made from scratch. No borrowed components with a different license
  • Supports all integer instructions except multiplication, division, push, pop
  • No vectors or floating point yet
  • Clock frequency 50 - 70 MHz depending on configuration
  • Six stages pipeline
  • Choice of 32-bit or 64-bit registers
  • 32 kB data memory, 64 kB code memory, 1023 entries call stack
  • Throughput is one instruction per clock cycle. Jump and branch instructions have a latency of 2 - 7 clock cycles. All other instructions have a latency of 1 clock
  • On-chip loader
  • On-chip debugger
  • On-chip event counter
  • RS232 serial interface for input and output (tunneled through USB cable)
  • Manual with full documentation
  • Test suite for self-test
  • Code examples provided
The softcore is published at https://github.com/ForwardCom/softcoreA

Manual for the softcore with full documentation at https://github.com/ForwardCom/softcoreA ... core_A.pdf


Version 1.11 of the ForwardCom standard is published at the same time.
It includes new instruction formats allowing instructions to have both a memory operand and an immediate operand. Branch instructions can now have a memory operand. A number of instructions have been modified. ForwardCom manual version 1.11: https://github.com/ForwardCom/manual/ra ... ardcom.pdf